1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a data transfer apparatus.
2. Description of the Related Art
In a data transfer apparatus, an operation module which issues a data transfer request accesses a memory controller via a network. A plurality of operation modules transmit command signals and data signals to the memory controller when issuing the data transfer requests. When a split transaction method is employed as a data transfer method, the transmission and reception of the command signals and the data signals are periodically independently controlled.
A write operation is described below in the data transfer apparatus wherein there are provided two operation modules and the memory connected to the memory controller is a dynamic random access memory (DRAM).
Assume a case where, in writing in the DRAM (write operation), the first and second operation modules issue write commands, and the network transfers a command signal of the first operation module to the memory controller before transferring a command signal of the second operation module to the memory controller.
In this case, if a data signal of the first operation module is output at an extremely late timing after the memory controller has received the command signal and accepted the data transfer request, the data transfer of the second operation module cannot be executed until the data transfer of the first operation module finishes in order to observe the order of writing.
That is, even if the data in the second operation module is already transmittable, the second operation module is put on standby until the data transfer of the first operation module finishes. Moreover, the network and the memory controller are also put on standby so that the data transfer is not executed. As a result, data transfer efficiency decreases.
On the other hand, there is a method wherein the network arbitrates the data transfer requests of the operation modules before the data in the first and second operation modules are ready. However, in this method, the DRAM has to secure a certain period of time from address notification accomplished by the transmission and reception of the command signals to writing of the data signals. Therefore, in this case, the standby state is generated until the data transfer to the DRAM even if the data signals have arrived at the memory controller. Thus, the efficiency of the data transfer decreases, and in order to prevent this, it is necessary to provide a buffer circuit in a system and increase the buffer size.
In a read operation (reading) as well, a problem similar to that in the write operation arises, and the whole system is put on standby, so that the data transfer efficiency decreases.
For example, Jpn. Pat. Appln. KOKAI Publication No. 2004-355271 has been disclosed as a technique that solves the above-mentioned problem. In the technique disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2004-355271, the whole data transfer apparatus needs to be under central control, so that system design becomes more difficult as the system scale increases. Moreover, accesses are based on a major cycle, and the transfer efficiency therefore decreases, particularly when there is a variation in data transfer amount between the modules.